First Look

Sigrity launches thermal/electrical co-simulation environment

By Bill Murray

01/28/10

According to Sigrity, its new PowerDC Thermal tool is the first to support the automatic co-simulation of thermal and electrical behavior, eliminating the iterative, manual simulate-and-analyze process necessitated by the traditional dual-simulator approach. The new tool operates at the board and package level, and comprehends chip data, too.

X-Fab launches industry’s first IC foundry process for high-performance optoelectronic applications

By Bill Murray

01/19/10

X-Fab’s new standard XO035 CMOS process targets Blu-ray and optical data communication markets with customizable PIN diode capability. The company claims that the process reduces total system cost by enabling users to integrate optoelectronic systems into a single chip, instead of the two chips required hitherto. SCDsource interviewed the company to dig below the press release.

Using formal for design space exploration

By Joachim Knäblein

11/16/09

The author discusses the application of formal verification tools to the temporal analysis of communication architectures. This SystemVerilog-based method enables analysis of the specification in terms of function and performance, and the author discusses how the design space can be explored at the specification level.

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News Analysis

Randal Bryant receives the 2009 Phil Kaufman Award

By Bill Murray

11/06/09

Mathematician receives award for seminal contributions in the field of verification. His breakthrough work on ordered binary decision diagrams (OBDD) – which provide a means to represent and reason about Boolean functions – form the computational basis for hardware verification and logic circuit synthesis. SCDsource reviews highlights from the award ceremony.

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First Look

Marvell launches “game-changing” ARM-based chips for consumer apps

By Bill Murray

10/21/09

Marvell’s Armada family of ARM-based system-on-chip (SoC) devices targets applications ranging from digital photo frames, through mobile devices, to high definition “big box” consumer products. The company designed the processors from ground up and combined them with its established base of multimedia and communications technologies to produce several chips, each with specific target markets. We also hear from leading analysts Tim Bajarin and Will Strauss.

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In My Opinion

Waving goodbye to phantom DRC errors

By Michael White

01/27/10

When migrating IP to new process nodes or different foundries, previously-waived DRC errors can create phantom DRC errors. Such phantoms can cost just as much time and effort to debug as real errors. Mentor’s Michael White posits an effective solution.

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Engineering Insights

Why AMCC adopted OVM – the expectations and the outcomes

By Bill Murray

01/21/10

AMCC’s Parag Goel and Pushkar Naik recently presented and published a paper “SystemVerilog + OVM: Mitigating Verification Challenges and Maximizing Reusability” which details their experiences in adopting and deploying the Open Verification Methodology (OVM). In this interview, they outline their reasons for OVM adoption, its primary benefits – especially in test case generation and reuse – and some enhancements that they’d like to see.

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Contributed Article

Chip synthesis solves the synthesis-to-P&R correlation problem

By Paul van Besouw

12/15/09

Chip synthesis optimizes placement and eliminates routing congestion at the RT-level before synthesizing to the gate level. It synthesizes and optimizes the whole chip, replacing block-by-block synthesis and post-synthesis chip assembly. Oasys Design Systems’ CEO describes how and shows the results.

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First Look

NXP targets 8/16-bit apps with low cost Cortex-M0 MCU

By Bill Murray

11/19/09

The LPC1100 flash-based 32-bit microcontroller family targets 8/16-bit applications. Compared to traditional 8/16-bit microcontrollers, it claims 40 to 50 percent smaller code size and up to 10X the performance. And it has a beginning price of 65 cents in 10,000-unit quantities. We also hear from iSuppli analyst, Jordan Selburn.

Right first time design needs a radical rethink

By Wes Hansford

10/23/09

Right-first-time design has been the Holy Grail of ASIC and SoC design for decades. But MOSIS’ Wes Hansford says it needs a radical rethink. An alternative approach can reduce the risk and cost of re-spins dramatically, and optimise the design.

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News Bytes

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Popular Special Technology Reports

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Imagination Technologies announced new audio and 3D graphics IP. META AXD is a full audio platform that delivers a complete multi-standard/multi-stream audio solution for SoC. It achieves its high performance by leveraging multi-threaded processing, in a shared memory, high-latency environment. All SoC audio processing can be off-loaded to the IP core, liberating CPU resources for other purposes. The IP supports common audio standards such as MP3, HE AAC, WMA, and surround sound up to 7.1.

POWERVR SGX545, the first and only DirectX 10.1 capable embedded graphics IP core. SGX545 supports OpenGL ES 2.x and OpenGL 3.2 for 3D graphics, and OpenCL 1.0 full profile capability for mobile and embedded applications. The IP achieves 40 million polygons per second and 1 Gpixels per second fill rate at 200MHz, and can drive HD screens with ultra smooth high frame rate 3D graphics content.

Marvell announced the world's first "quadruple" core processor for applications utilizing the ARM instruction set. The core utilizes the same CPU architecture that the company built from ground up for the ARMADA 500 and 600 SoC. The quadcore can deliver gigahertz-plus performance per core and is designed for mass consumer market products and high volume gaming applications. The announcement follows the release of the Armada 610, the latest addition to the Armada SoC series. The 610 has a gigahertz-class CPU, integrated 1080p full-HD encode and decode, and 3D graphics. It is targeted at mobile communications, information and entertainment products. See also SCDsource article Marvell launches “game-changing” ARM-based chips for consumer apps.

Real Intent is shipping its Ascent Lint Version 1.2. It offers new rule support for low-noise and high performance SoC, encompassing rules from STARC Policy, Verilog and SystemVerilog Gotchas, Reuse Methodology Manual (RMM), Principles of Verifiable RTL Designs, and rules based on Real Intent industry expertise. The rules cover legal but dubious modeling; simulation and synthesis semantics differences; subset restrictions to enforce modeling clarity and reduce complexity; opportunities to improve simulation performance; operations with hidden or expensive implementation costs; downstream tool flow issues; network and connectivity checks for clocks, resets, and tristate-driven signals; module partitioning rules; and testability.