Actel offers power-driven layout and analysis

By Richard Goering

11/20/07

To help designers predict and reduce dynamic power consumption in its programmable devices, Actel Corp. this week (Nov. 19) introduced new capabilities for the SmartPower analysis tool in its Libero Integrated Design Environment (IDE). Improvements include power-driven layout, power “profiles” based on actual use models, and battery life estimation.

SmartPower has been part of Libero for the past few years, noted Jim Davis, vice president of software engineering at Actel. “We wanted to add some further capabilities to SmartPower to enhance the capability of designers to understand where their sources of power consumption are,” he said.

The announcement follows by one week Actel’s introduction of a 4×4 mm package for its Igloo low-power FPGAs, claimed to be the smallest package for any programmable logic device. Actel is currently offering its 30,000-gate Igloo AGL030 device in this package.

The new software capabilities are available with the SmartPower utility in the newly-released Libero IDE version 8.1. Power-driven layout is available for Actel’s ProASIC3, Igloo, and mixed-signal Fusion device families. It claims to provide 13 to 30 percent power savings by reducing the capacitive loading of nets.

“Most of the improvements come in placing things in such a way that it will take fewer routing resources to get the job done,” Davis said. Much of the net capacitance reduction comes from the way clock distribution networks are laid out, he said. If the placer packs enough logic onto rows and columns, he noted, there are fewer rows and columns that need to be powered up.

Power-driven layout is an automated capability that’s enabled by checking a box in the Libero graphical user interface. If users don’t provide switching activity information, the layout tool will make its own estimates. Designers can also tell the tool to make assumptions about switching activity. But the most accurate results come when users provide switching activity information from simulation, Davis said.

The power-driven layout does have a tradeoff – it typically “perturbs” device performance by one or two percent, Davis said. It also affects only net capacitance, not gates, I/Os or memories. The power savings it produces thus depend on how significant net capacitance is in a given device. In Igloo devices, for instance, net capacitance is a higher percentage of total dynamic power than in ProASIC 3 devices, so the savings would be greater for Igloo FPGAs.

Another improvement to SmartPower has to do with power “profiles.” Defined by the user, a power profile is the percentage of time that a device will be in a combination of modes, including active, standby, or Actel’s “flash freeze” (which stops the clocks, puts I/Os in a known state and preserves the state of the SRAMs and registers). For example, a user could determine that a given device will be in active mode 50 percent of the time, flash freeze mode 40 percent of the time, and sleep mode 10 percent of the time, and get a power calculation across that use model.

“Most analysis tools tell you a device is running and using this much power, but that’s not the way most devices work,” Davis said. “A cell phone might be off most of the time or be in some monitor mode.” With the new power profile capability, he noted, users can also define “custom” modes with variable clock frequencies.

SmartPower has also added a battery life estimation capability. To use it, designers input the desired battery’s current capacity as well as the power profile of the FPGA. SmartPower then displays the expected battery life. It’s based on a “simple linear degradation model,” Davis said.

Also new is a hazard or glitch analysis that identifies spurious transitions that contribute to higher power consumption. A report highlights the number of functional transitions, and the number of hazards and their associated power. Finally, a new cycle-accurate power report shows the peak power per clock cycle, helping users identify and design for worst-case scenarios.

Actel’s Libero IDE 8.1 is available on Windows and Linux platforms for $2,495. SmartPower works for all Actel devices, although the power-driven layout capability doesn’t work for Actel’s legacy antifuse device families.

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