Responding to one of the key challenges facing established EDA vendors, Synopsys this week (March 10) is announcing a "multicore initiative" to re-architect its most commonly-used IC design and verification products to run on multicore platforms. Synopsys is also rolling out new multi-threading capabilities for its HSpice circuit simulator.

 

While a number of recent startups have fielded IC design and verification tools built from scratch for multicore platforms, established EDA vendors face the challenge of retrofitting existing tools. Gary Smith, chief analyst at Gary Smith EDA, has identified the rewriting of tools for parallel computing as the issue with the "largest potential impact on the competitive makeup of EDA" in 2008. Smith said last year that rewriting a large CAD application for multi-processing can be a three-year process.

 

Synopsys is stepping up to the challenge, promising multicore versions of the following products in 2008:

 

 

Aside from this week's HSpice announcement, Synopsys is not offering a specific timetable for tool releases. In most cases, Synopsys will offer multi-threaded versions of these tools, although multi-threading will not necessarily be the company's only approach to preparing products for multicore platforms.

 

"It's a pretty broad initiative," said Steve Smith, senior director of product platform marketing at Synopsys. "It's going to cover verification, implementation, and manufacturing, and you'll see a number of announcements over the next few months." Synopsys felt the need to respond, he said, because most processors these days have 2, 4, or 8 cores.

 

"Historically, we've relied on increasing processor clock speeds to get additional compute power, but with the advent of multicore processors, it's a new paradigm," Smith said. "To get an additional performance boost, we need to be able to take advantage of multicore processors in a different way."

 

Smith noted that Synopsys has some applications that use distributed processing over networks of workstations. Examples include the VCS simulator, which can spawn independent simulation jobs across a compute farm, and PrimeTime, which can use distributed processing to analyze multiple process corners and operating modes. But these applications are not multi-threaded and are not currently optimized for multicore processors on a single die with shared memory.

 

"We need to adjust some of our algorithms," Smith said. "You might have a two-core system with one set of memory, so we're addressing that." Smith noted that Synopsys engineers are having to take such considerations as network bandwidth and storage capacity into account, and that development for multicore "becomes almost an IT problem." As such, he noted, that's an active partnership between Synopsys' IT group and R&D organization to resolve some of these challenges.

 

But it's not a three-year rewrite process, Smith said. In fact, he said, Synopsys hasn't had to actually "rewrite" any of its tools. The amount of effort depends on the application. "We're finding that some tasks lend themselves naturally to multi-threading, and others do not," he said. "We're working with the hardware vendors and the compute platform vendors, and they've all provided help with multi-threaded compilers and debuggers."

 

Synopsys does have a few applications that are multi-threaded today. These include the Hercules IC physical verification product and Proteus OPC tool suite. The model evaluation capability in HSpice has been multi-threaded since September 2006. What's new this week is multi-threading for the HSpice matrix solver.

 

With the proliferation of multicore CPUs in workstations, the competitive pressure to fully exploit multicore capabilities has grown. The capacity demands of 65 nm and 45 nm IC designs have further driven the demand for multicore.

 

A number of announcements within the past year have emphasized multi-threading or other approaches that support multicore platforms. For example, startup CLK Design Automation rolled out a multi-threaded static and statistical timing analyzer in 2007, and Extreme DA quickly followed suit. Pyxis Technology's NexusRoute "yield-driven" autorouter, introduced in September 2007, offers multi-threading. Atoptech's Aprisa, the newest netlist-to-GDSII design suite, offers parallel processing over multiple workstations or multicore CPUs.

 

What's not yet clear is whether multi-threading is the best way to exploit multicore capabilities. Critics such as Gary Smith argue that threading is a poor approach to parallel processing that doesn't scale well. Magma Design Automation last year rolled out a multi-processing and multicore capability for its Quartz-DRC design rule checker that uses a "streaming dataflow-based architecture" instead of multi-threading.

 

Synopsys isn't committed to any particular approach. "In some cases multi-threading does make sense, in other cases, we'll likely use other techniques," Smith said. "Multi-threading doesn't apply to all algorithms in EDA. Other concepts include distributed processing, design partitioning, data partitioning, and pipelining." One technique Synopsys is investigating, he said, collapses multiple tasks such as OPC and mask data preparation into a single pipeline.

 

Threading does have its limits. With HSpice, said Geoffery Ying, director of marketing for mixed-signal simulation products at Synopsys, "we see pretty good scaling to 4 to 8 [cores], and beyond that there are diminishing returns." Amdahl's Law, he noted, mandates that "you cannot scale forever. Overhead will eventually catch up."

 

With HSpice's multi-threaded matrix solver, Ying said, 4 cores will typically provide a 2 to 2.5X speedup over a single core, and 8 cores might provide a 4.5X to 5X speedup. After that, the speedup "starts to flatten out." Ying said Synopsys doesn't have conclusive data on 16-core machines.

 

 

 

Synopsys has also improved the HSpice solver, however, and there's a speedup from that as well, Ying said. The newest version of HSpice claims improvements in the symbolic DC operating point convergence algorithm, transient time-step control, netlist parsing and model performance.

 

Another question that comes up with multicore support is licensing. Smith said that Synopsys is considering licensing models that provide a better way to "take advantage of multicore" than a conventional per-CPU license. One possibility he acknowledged is some form of thread-based licensing. Fast Spice provider Nascentric introduced thread-based licensing in January 2008.

 

Smith said that Synopsys will be making multicore announcements throughout the year, but expects most announcements to be completed by summer. He said the software will support Intel, AMD, and Sparc multicore platforms. Most current Synopsys RTL-to-GDSII tools are included in the multicore initiative, but Synopsys does not intend to retrofit older placement and routing tools, Smith said.

 

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