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First Look

Sigrity launches thermal/electrical co-simulation environment

By Bill Murray

01/28/10

According to Sigrity, its new PowerDC Thermal tool is the first to support the automatic co-simulation of thermal and electrical behavior, eliminating the iterative, manual simulate-and-analyze process necessitated by the traditional dual-simulator approach. The new tool operates at the board and package level, and comprehends chip data, too. Read more...

In My Opinion

Waving goodbye to phantom DRC errors

By Michael White

01/27/10

When migrating IP to new process nodes or different foundries, previously-waived DRC errors can create phantom DRC errors. Such phantoms can cost just as much time and effort to debug as real errors. Mentor’s Michael White posits an effective solution. Read more...

Engineering Insights

Why AMCC adopted OVM – the expectations and the outcomes

By Bill Murray

01/21/10

AMCC’s Parag Goel and Pushkar Naik recently presented and published a paper “SystemVerilog + OVM: Mitigating Verification Challenges and Maximizing Reusability” which details their experiences in adopting and deploying the Open Verification Methodology (OVM). In this interview, they outline their reasons for OVM adoption, its primary benefits – especially in test case generation and reuse – and some enhancements that they’d like to see. Read more...

First Look

X-Fab launches industry’s first IC foundry process for high-performance optoelectronic applications

By Bill Murray

01/19/10

X-Fab’s new standard XO035 CMOS process targets Blu-ray and optical data communication markets with customizable PIN diode capability. The company claims that the process reduces total system cost by enabling users to integrate optoelectronic systems into a single chip, instead of the two chips required hitherto. SCDsource interviewed the company to dig below the press release. Read more...

Contributed Article

Chip synthesis solves the synthesis-to-P&R correlation problem

By Paul van Besouw

12/15/09

Chip synthesis optimizes placement and eliminates routing congestion at the RT-level before synthesizing to the gate level. It synthesizes and optimizes the whole chip, replacing block-by-block synthesis and post-synthesis chip assembly. Oasys Design Systems’ CEO describes how and shows the results. Read more...

First Look

NXP targets 8/16-bit apps with low cost Cortex-M0 MCU

By Bill Murray

11/19/09

The LPC1100 flash-based 32-bit microcontroller family targets 8/16-bit applications. Compared to traditional 8/16-bit microcontrollers, it claims 40 to 50 percent smaller code size and up to 10X the performance. And it has a beginning price of 65 cents in 10,000-unit quantities. We also hear from iSuppli analyst, Jordan Selburn. Read more...

Contributed Article

Using formal for design space exploration

By Joachim Knäblein

11/16/09

The author discusses the application of formal verification tools to the temporal analysis of communication architectures. This SystemVerilog-based method enables analysis of the specification in terms of function and performance, and the author discusses how the design space can be explored at the specification level. Read more...

News Analysis

Randal Bryant receives the 2009 Phil Kaufman Award

By Bill Murray

11/06/09

Mathematician receives award for seminal contributions in the field of verification. His breakthrough work on ordered binary decision diagrams (OBDD) – which provide a means to represent and reason about Boolean functions – form the computational basis for hardware verification and logic circuit synthesis. SCDsource reviews highlights from the award ceremony. Read more...

In My Opinion

Right first time design needs a radical rethink

By Wes Hansford

10/23/09

Right-first-time design has been the Holy Grail of ASIC and SoC design for decades. But MOSIS’ Wes Hansford says it needs a radical rethink. An alternative approach can reduce the risk and cost of re-spins dramatically, and optimise the design. Read more...

News Analysis

Mentor announces next step in Nucleus breakout strategy

By Bill Murray

10/22/09

Supporting its strategy of breaking the Nucleus RTOS out of its beach-head in mobile phone baseband applications and into applications processors, Mentor has collaborated with ARM to support the operating system with the ARM RealView Development Suite. The move positions Mentor to address automotive and medical applications, as well as additional mobile applications. Read more...