PDF CEO calls for restricted layouts

By Richard Goering


SAN JOSE, Calif. – The key to chip design success at 32 nm and below will be “restricted patterning,” according to John Kibarian, president and CEO of PDF Solutions. At an International Conference on Computer-Aided Design (ICCAD) keynote speech Nov. 8, Kibarian said the best way to produce manufacturable ICs will be to restrict chip layouts to 10 or 20 pre-characterized, regular patterns.

“We tried to maintain designer freedom for a long time, and as an industry we’ve paid a tremendous cost,” Kibarian said. “It’s a cost we won’t be able to afford at 32 nm and 22 nm. We’re going to have to go to restricted layouts.”

Restricted patterning won’t require design tradeoffs, Kibarian claimed. Instead, he argued, it will lead to a chip area reduction, elimination of many design for manufacturability (DFM) rules and requirements, improved leakage, reduced functional and parametric variability, and lowered costs for library and intellectual property (IP) development. He said it will greatly reduce the time required to design 32 nm ASICs, and will permit dry immersion lithography at 45 nm and below, reducing manufacturing costs.

Kibarian’s speech didn’t mention PDF’s May 2007 acquisition of Fabbrix, a startup from Carnegie Mellon University that developed libraries of “logic bricks” that contain regular structures built from lithography-friendly shapes. As a result of that acquisition, PDF sells a design kit called pdBrix, which implements the type of restricted patterning that Kibarian’s keynote described.

After the speech, Kibarian noted that PDF has two customers evaluating pdBrix, but that it hasn’t gone into production yet. He acknowledged that the purchase of Fabbrix represented a “huge change” for the company as a DFM advocate and provider, but he said that pdBrix is “synergistic” with PDF’s existing yield analysis and characterization business.

Freedom isn’t free

In his keynote, Kibarian argued that the way we’ve defined designer “freedom” is prohibitively expensive and that the situation will become worse. Designer freedom today, he said, means that design rules constrain only what is not allowed, designers can implement a wide variety of transistor patterns, and large standard cell libraries support a range of design styles. “We have the idea that we can use transistors in any way whatsoever, and we support that in the design flow,” he said.

As a consequence of this freedom, he said, process R&D costs and design costs are escalating quickly, and library and IP qualification costs are growing at an accelerated rate. Kibarian said that library and IP cost per design will increase 125 percent from 65 nm to 32 nm. “This is a major train wreck,” he said. “Every executive I talk to worries about this.”

Meanwhile, Kibarian said, the DFM design rule set has doubled in size over three process generations, but only a handful of the design rules actually have an impact on yield. “We started making test vehicles to characterize all these design rules,” he said. “10 to 20 percent of recommended rules matter and 80 to 90 percent are worthless at the end of the day. But I guarantee that all will impact area and performance.”

Designer freedom also carries a cost in transistor performance, Kibarian said. For example, he claimed, Ioff (off current) variance can increase two orders of magnitude due to layout effects. Parametric yield loss is growing due to transistor variability, he said.

Kibarian also noted that design costs are increasing by 70 percent per node, and that the cost to design a chip at 65 nm is twice the cost to design a chip at 130 nm. This hurts silicon startups, he said, because fewer and fewer chips have a broad enough market to justify the design costs. And the number of tapeouts is going down as process sizes shrink, Kibarian said – one prediction is that only six companies will have more than 10 tapeouts at 22 nm.

“The cost of trying to give people freedom is high, and it’s been going up in double digits from generation to generation,” he said. “The industry needs to take a step back.” Arguing that freedom could limit the benefits of new process nodes and waste billions of dollars in process technology development, Kibarian said that “you can’t have the flexibility to use transistors in any way you want.”

A new design approach

A new approach to design, Kibarian said, should “eliminate DFM. Designers shouldn’t have to worry about physics.” It should also achieve improved performance by reducing transistor variations, eliminate the 15 to 25 percent logic area penalty associated with DFM design rules, and improve portability, he said.

A “restricted approach to increase freedom,” as Kibarian put it, will map circuits into predictable, pre-characterized patterns, while achieving the density and performance of standard cells. The first step, he said, is to stop defining what’s not allowed and start defining what is allowed. “We’re going to have to define the patterns we can use, and it’s going to be a very small number, no more than 10 or 20,” he said. “To make that work, we’re going to have to use higher functionality cells.”

The place to start, Kibarian said, is with SRAM patterns. Design logic should have restrictive patterning compatible with SRAM lithography, he said. “We’ve got to have a restricted set of layout patterns that are very regular,” he said.

Restricted patterning, Kibarian said, will eliminate most layout dependence and greatly reduce transistor variability. He said it will reduce chip area by 15 to 25 percent, compared to standard cells based on restricted design rules (RDRs). It will allow improved leakage and power/performance variability, even compared to RDRs. It will also greatly reduce library and IP development costs, he said.

Restricted patterning will impact two points in the design flow, Kibrarian said. One is synthesis, which will need to be optimized for large functional blocks rather than gates or flip-flops. The other is the signoff flow, where optical proximity correction (OPC) and design rule checking (DRC) will be greatly simplified, and the need to repair lithography hot spots eliminated. “You should never need OPC verification,” he said. “We don’t put SRAMs through an OPC toolset at the end. We make the layout OPC correct in the first place.”

As an example, Kibarian pointed to a 65nm ARM926EJ design that was implemented with 20 fixed-size logic bricks from the pdBrix design kit. He said the design had the same block footprint as the original standard cell implementation, had equivalent performance, and was functional on first silicon.

An audience member asked Kibarian how restricted patterning would impact large EDA vendors. “I haven’t given a lot of thought to what they should do,” he replied. “For suppliers, it’s good for things to be more complicated, but we’re killing ourselves because we’ll have a smaller number of customers over time.”

Lou Scheffer, Cadence fellow, spoke from the audience to note that EDA vendors are making it possible, but not required, to follow restricted design rules. Making it mandatory “would be committing commercial suicide [for EDA vendors],” he said.

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