Structured ASICs add ‘free’ Tensilica cores

By Richard Goering


Hoping to greatly expand the marketplace for its structured ASICs, eASIC Corp. is claiming to provide its customers with Tensilica processor cores without cost. The agreement between the two companies makes customized systems-on-chip (SoCs) cost-competitive with FPGA-based embedded systems, eASIC says.

As a result of a partnership announced this week (Nov. 26), eASIC will provide free access to Tensilica Diamond processors, including three 32-bit controllers, two 32-bit CPUs, and two DSP cores. Customers pay no up-front costs and pay no extra charge for the finished devices, according to eASIC – but they’ll still need to purchase software development tools from Tensilica.

The companies are hoping the agreement will spark renewed interest in the structured ASIC marketplace, which has seen retreats from providers including Lightspeed Semiconductor, LSI Logic, and NEC. But a number of other providers remain, and analyst forecasts generally point to continued growth, although structured ASICs remain a small part of the overall ASIC marketplace.

Ronnie Vashishta, eASIC CEO, said the agreement gives designers access to Tensilica cores on any eASIC device, which carry no mask costs and impose no minimum order quantities. “The upfront cost to the customer is down to zero, which I think is quite unique,” he said. Customers can order a prototype volume of devices with Tensilica cores, he noted, and then ramp up to high volumes with the same device without having to go through a design migration.

eASIC is paying Tensilica for the cores, and is hoping that increased volumes will make up for the cost of the cores. “The business model we’ve been able to achieve with Tensilica enhances and grows our market such that we’re able to pass the cores on with no additional cost to the customer, because our business grows,” Vashishta said.

“Tensilica is paid as production volumes ramp up,” noted Steve Roddy, vice president of marketing at Tensilica. “I assume eASIC business will expand as the result of serving a broader number of customers, with a broader array of IP [intellectual property].”

eASIC also offers an ARM926EJ processor, but there is a licensing fee for that processor. The Tensilica agreement is thus the first of its kind for eASIC, Vashishta said. Tensilica, for its part, has distribution agreements with other silicon vendors, but the eASIC agreement marks the company’s first move into the structured ASIC market, Roddy said. It’s also the first time that Tensilica cores have been available for no up-front cost.

Roddy said that Tensilica is seeing customer interest in structured ASICs. This is because the cost of standard-cell implementations is growing, and there are limitations to what one can achieve with an FPGA, he said. “We want to get our architecture as broadly used as possible, so we want to try to grab a share of a market that looks like it’s ready to increase in terms of the number of design starts,” he said.

“Structured ASIC revenues and design starts have been down for the last two years, but we are seeing select players have success in the market,” said Bryan Lewis, analyst at Gartner Dataquest. “Altera recently won a number of new design wins with HardCopy, and we are hearing others talk about a resurgence of activity after the big fallout a couple years ago. There is clearly demand for low-cost ASICs for those who can find the right recipe.”

eASIC announced its current 90 nm Nextreme family in November 2006. It includes devices ranging from 350,000 to 5 million gates, supports 350 MHz system performance, and uses a design flow from Magma Design Automation. By employing FPGA-like logic cells and via-layer customizable routing, eASIC eliminates mask costs and promises devices in under 4 weeks.

Tensilica offers both Diamond off-the-shelf processor cores and configurable Xtensa processor cores. Diamond cores available with eASIC devices include:

  • 106Micro — a cacheless 32-bit RISC controller with built-in DSP
  • 108Mini – a cacheless 32-bit RISC controller with built-in DSP
  • 212GP – a mid-range 32-bit RISC controller
  • 232L – a mid-range 32-bit CPU with Memory Management Unit (MMU)
  • 570T – a high-end 32-bit CPU core
  • 545CK – a high-performance DSP core
  • 330HiFi – a low-power, 24-bit audio DSP processor

While other vendors have been unsuccessful with structured ASICs, Vashishta said eASIC is “different” because it can offer zero mask costs and no minimum order quantities. “The last piece of the pie is IP,” he said. “We need to have IP available, and that’s why the Tensilica announcement is so important to us. They’re already an established IP provider with a large user base, and they have experience with software development tools. We’re able to hit the ground running by bringing that kind of provider into our ecosystem.”

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